DocumentCode
3774612
Title
The Intel® Xeon® processor E5 family architecture, power efficiency, and performance
Author
Jeff Gilbert;Mark Rowland
fYear
2012
Firstpage
1
Lastpage
25
Abstract
Presents a collection of slides covering the following topics: Sandy Bridge core; SNB-EP performance; Thurley platform; CPU; DRAM; and memory latency optimization.
Keywords
"Microprocessors","Optimization","Benchmark testing","Energy efficiency","Power system management"
Publisher
ieee
Conference_Titel
Hot Chips 24 Symposium (HCS), 2012 IEEE
Type
conf
DOI
10.1109/HOTCHIPS.2012.7476501
Filename
7476501
Link To Document