• DocumentCode
    3775351
  • Title

    The IBM power edge of Network™ processor: A wire-speed system-on-a-chip with 16 Power™ cores / 64 threads and optimized HW acceleration

  • Author

    Jeffrey D. Brown;Sandra Woodward;Brian Bass;Charlie Johnson

  • Author_Institution
    IBM Corporation, USA
  • fYear
    2010
  • Firstpage
    1
  • Lastpage
    20
  • Abstract
    Presents a collection of slides covering the following topics: Network processor; IBM power edge; wire-speed system-on-a-chip; interconnect architecture; PowerPC processing element architecture; DDR3 DRAM controller; accelerator architecture; accelerator interface; compression/decompression; crypto data mover; XML engines; packet processor architecture; and PCI-Express.
  • Keywords
    "Program processors","Process control","Random access memory","Cryptography","XML","Computer architecture","System-on-chip"
  • Publisher
    ieee
  • Conference_Titel
    Hot Chips 22 Symposium (HCS), 2010 IEEE
  • Type

    conf

  • DOI
    10.1109/HOTCHIPS.2010.7480073
  • Filename
    7480073
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3775351