Performance evaluation of FIR filters using digit serial architectures

In FIR Filter design many architectures and algorithms been proposed for the design of low complexity parallel and serial Multiple Constant Multiplication (MCM) operation. MCM is one of the way to implement several constant variable multiplications with input data using adders, subtractor and shifters. But these designs cannot achieve tradeoff between area, delay and power. The digit serial MCM design can be one of the alternatives to implement MCM. By varying the digit size better results can be achieved. In this paper, the problem of reducing the gate level area in digit serial MCM design architectures with optimization algorithms and digit size variation effect is also studied. Operational results show the competence of the algorithm and digit serial architecture in the design of MCM and finite impulse response filter.