Fully delay and multiple stuck-at faults testable FSM design

Development of nanometer technologies increases demands to logical circuit testability. It is not enough to test stuck-at faults at gate poles of a circuit it is necessary to test multiple stuck-at faults at gate poles along with delay faults of a logical circuit. In this paper we show that it is possible to derive the sequential circuit from a transition table of a finite state machine (FSM) which has the short test detecting all multiple stuck-at faults at the gate poles of the sequential circuit, and a delay of each circuit path is detectable. Some structural and test simplifications are suggested.