Modification of the architecture of a distributed arithmetic

Distributed arithmetic has been widely used for area-time efficient implementation of inner products. It is a bit-serial computational operation that forms an inner product of a pair of vectors in a single direct step. If the word length of the vectors is large, the sequential implementation of the distributed arithmetic require a large number of steps. This paper proposes a way to reduce the number of steps. It is offered to refuse the sequential analysis of bit slices. Instead, the contents of the memory are assigned sequentially combinations of bit slices.