A novel low-cost interface design for SystemC and SystemVerilog Co-simulation

Based on the high-level abstract Golden Model in SystemC and UVM in SystemVerilog, the co-simulation method can effectively reduce the complexity of SoC verification, but how to design the interface between the two languages is the key to improving the efficiency of verification. A novel interface based on DPI is proposed in this paper. The interface adopts a two-stage structure and includes an environmental configuration unit and a protocol conversion unit. They are respectively realized in the two languages domains. Furthermore, to increase the simulation speed, the timing synchronization unit and stimulus import unit are realized in SystemC domain. The experiment results show that under the same configuring conditions and same test stimulus, compared to UVMC co-simulation library provided by Mentor Company, the interface proposed in this paper has same functional coverage while simulation time is reduced by about 20%, which has a significant advantage in performance.