• DocumentCode
    3781290
  • Title

    A DPA resistant dual rail Préchargé logic cell

  • Author

    Xiao Pang;Jing Wang;Chenxu Wang;Xinsheng Wang

  • Author_Institution
    Microelectronics Center, Harbin Institute of Technology at Weihai, Weihai 264209, China
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    This paper presents a novel differential pass-transistor precharge logic (DPPL) based on the complementary pass-transistor logic (CPL). In the aspect of circuit-level countermeasure, the power consumption of DPPL is more constant. The DPPL also solves the problem of early propagation effects (EPE) effectively and has a relatively small area overhead compared to the wave dynamic differential logic (WDDL). The power constancy and DPA resistant capability of DPPL are evaluated by SPICE simulation in this paper. The results show that the power constancy and DPA resistant capability of DPPL are superior to WDDL.
  • Keywords
    "Power demand","MOSFET","Resistance","Integrated circuit modeling","Logic gates","Analytical models"
  • Publisher
    ieee
  • Conference_Titel
    ASIC (ASICON), 2015 IEEE 11th International Conference on
  • Print_ISBN
    978-1-4799-8483-1
  • Electronic_ISBN
    2162-755X
  • Type

    conf

  • DOI
    10.1109/ASICON.2015.7517071
  • Filename
    7517071