Research of segmented 8bit voltage-mode R-2R ladder DAC

Modeling for voltage-mode R-2R ladder digital to analog converter (DAC) is introduced in this paper. By analyzing the mismatch of resistors in ladder, the DNL and INL calculation expression are obtained. In order to achieve a higher accuracy, segmentation is used in DAC. Five different segmentation methods are compared and 3+5 segmentation structure is chosen to achieve best DNL and INL performance. For post calibration, a code-dependent current consumption expression is derived from the input impedance of R-2R ladder. A 3+5 segmented DAC based on this modeling is implemented in a standard 0.18μm CMOS process. The post simulation results show that DNL and INL are bounded at 0.30 and 0.32LSB.