A 10b, 0.7ps resolution coarse-fine time-to-digital converter in 65nm CMOS using a time residue amplifier

This paper presents a TA based coarse-fine TDC with high resolution. The new design contains a half-pass judger to measure the relative position of the stop edge in the subrange of the delayed sequence. The extra operation helps to limit the range of time residue sent to the fine stage by one half. With the limitation, TA can achieve a high gain, ensuring the two-stage TDC with a high resolution. Besides, a new MUX structure is designed, and the signal ports are well arranged to improve the reaction speed and to reduce the power consumption. Experiment results show that resolution of the proposed circuit is 0.7ps, and the measurement range can reach 1ns. The DNL and INL are measured as 0.5LSB and 2LSB, respectively. Better linearity can be achieved by using INL lookup table and adding compensated blocks.