A /spl beta/-error elimination in the translinear reduction of the "log-antilog" multiplier/divider

A new type of the one-quadrant analog multiplier/divider based on the translinear reduction of the ´log-antilog" (TLRLA) multiplier/divider circuit is presented in this paper. A new technique for the error elimination due to the finite current gain /spl beta/ of the used bipolar junction transistors (BJTs) is described. By adding seven BJTs (three emitter followers and two simple current mirrors) to the classical TLRLA multiplier/divider; a significant improvement in accuracy is achieved. The linearity error is smaller than 0.45% of full scale, and relative error is smaller than 1.2% of full scale, in the 0 A to 3 mA input current range, and in the 0 A to 9 mA output current range. These simulated results have been achieved with a 3 V supply.