Efficient interconnect timing analysis via piecewise linear technique

In this paper the application of the piecewise linear technique (PWL) to the timing analysis of circuit interconnects is presented. An RC network described by a set of linear ODEs is used to model the interconnect circuitry. The network analysis proceeds in terms of the waveform relaxation (WR)-based iterations, but the subsequent waveforms are obtained very effectively with explicit formulas as opposed to standard approaches used for ODEs. All the signals in the RC network take the PWL form that is assured by a unique non-iterative approximation procedure. The analysis algorithm is shown to be absolutely stable for standard RC trees. The model provides a performance approaching that of SPICE with a speed-up of up to 100 or more for larger networks. Some timing analysis examples for the RC trees are presented. Extensions of the method and future plans are given in summary.