A 100 Gb/s transceiver with GND-VDD common-mode receiver and flexible multi-channel aligner

Author

Tanaka, K. ; Fukaishi, M. ; Takeuchi, M. ; Yoshida, N. ; Minami, K. ; Yamaguchi, K. ; Uchida, H. ; Morishita, Y. ; Sakamoto, T. ; Kaneko, T. ; Soda, M. ; Kurisu, M. ; Saeki, T.

Author_Institution

NEC Corp., Kanagawa, Japan

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

264

Abstract

A 5 Gb/s 20-channel transceiver uses 0.13 /spl mu/m 1.5 V CMOS technology. The sampling amplifier recovers /spl plusmn/100 mV 90 ps data over 0-1.5 V common-mode range. A flexible multi-channel aligner and full-digital CDR (clock/data recovery) architecture are used.

Keywords

CMOS integrated circuits; amplifiers; signal sampling; synchronisation; telecommunication cables; telecommunication channels; telecommunication transmission lines; transceivers; 0 to 1.5 V; 0.13 micron; 1.5 V; 100 Gbit/s; 5 Gbit/s; 90 ps; CMOS technology; GND-VDD common-mode receiver; common-mode range; data recovery; flexible multi-channel aligner; full-digital CDR architecture; full-digital clock/data recovery architecture; sampling amplifier; transceiver; CMOS technology; Clocks; Counting circuits; Energy consumption; Master-slave; Phase locked loops; Pulse amplifiers; Sampling methods; Transceivers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.993037

Filename

993037