A surface potential model for predicting substrate noise coupling in integrated circuits

Caution must be taken when designing circuits so that noise injected to and transmitted through the substrate does not reach and degrade the performance of sensitive circuitry present on the chip. In this paper we present a simple analytic substrate model for evaluating substrate noise coupling. The model can handle an arbitrary number of aggressor and victim devices on a multi-layered substrate with either biased or floating backside. The model has been validated by finite element calculations and measurements on test structures manufactured in a 0.35 /spl mu/m CMOS process, and it is shown that the model gives an accurate description of the substrate noise coupling. For example, the noise suppressing properties of guard rings have been evaluated.