DocumentCode
383334
Title
Inherently planar fully depleted SOI isolation
Author
Burns, J. ; Costa, C. ; Warner, K.
Author_Institution
Lincoln Lab., MIT, Lexington, MA, USA
fYear
2002
fDate
7-10 Oct 2002
Firstpage
103
Lastpage
104
Abstract
The authors indicate that SOI devices can be isolated by an inherently planar technique that simplifies gate lithography and reduces field enhancement at island edges without the complexities of an STI process by using the low temperature oxide-oxide bond process.
Keywords
field effect transistors; isolation technology; lithography; rapid thermal annealing; scanning electron microscopy; silicon-on-insulator; FDSOI transistors; FET; SEM; SOI devices; field enhancement; fully depleted SOI isolation; gate lithography; island edges; low temperature oxide-oxide bond process; planar technique; rapid thermal annealing; Electron microscopy; FETs; Isolation technology; Lithography; Rapid thermal annealing; Silicon on insulator technology;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, IEEE International 2002
Print_ISBN
0-7803-7439-8
Type
conf
DOI
10.1109/SOI.2002.1044436
Filename
1044436
Link To Document