A floating-point unit using stochastic arithmetic compliant with the IEEE-754 standard

Author

Chotin, Roselyne ; Mehrez, Habib

Author_Institution

LIP6/ASIM Lab., Univ. Pierre et Marie Curie, Paris, France

Volume

2

fYear

2002

fDate

2002

Firstpage

603

Abstract

In this paper, we present CESTAC, a method to control round-off errors in floating-point scientific computation, based on stochastic arithmetic. The real time use of this method suffers from a bottleneck of software calculations. This paper gives a hardware alternative that would significantly accelerate the computation. The proposed hardware architecture has two parts: a standard floating-point unit (FPU) and a unit dedicated to the control of round-off errors.

Keywords

IEEE standards; circuit CAD; floating point arithmetic; integrated circuit design; integrated circuit modelling; logic CAD; logic simulation; roundoff errors; stochastic processes; 32 bit; CESTAC computation hardware acceleration; CESTAC method real time software calculation bottleneck; FPU; IEEE-754 standard; arithmetic operations; floating-point scientific computation; floating-point units; round-off error control; stochastic arithmetic; Acceleration; Central Processing Unit; Computer architecture; Costs; Digital arithmetic; Floating-point arithmetic; Hardware; Laboratories; Roundoff errors; Stochastic processes;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2002. 9th International Conference on

Print_ISBN

0-7803-7596-3

Type

conf

DOI

10.1109/ICECS.2002.1046241

Filename

1046241