A Low Temperature Fully Lithographic Process For Metal–Oxide Field-Effect Transistors

We report a low temperature ( ~ 100?C) lithographic method for fabricating hybrid metal oxide/organic field-effect transistors (FETs) that combine a zinc-indium-oxide (ZIO) semiconductor channel and organic, parylene, dielectric layer. The transistors show a field-effect mobility of (12?0.8) cm² V^-1 s^-1, on/off ratio of 10⁸ and turn-off voltage of V_off = -1 V. This work demonstrates that organic and inorganic layers can be deposited and patterned using a low temperature budget, integrated lithographic process to make FETs suitable for large area electronic applications.