• DocumentCode
    3848622
  • Title

    The SARC Architecture

  • Author

    Alex Ramirez;Felipe Cabarcas;Ben Juurlink;Mauricio Alvarez Mesa;Friman Sanchez;Arnaldo Azevedo;Cor Meenderinck;Catalin Ciobanu;Sebastian Isaza;Gerogi Gaydadjiev

  • Author_Institution
    Barcelona Supercomputing Center
  • Volume
    30
  • Issue
    5
  • fYear
    2010
  • Firstpage
    16
  • Lastpage
    29
  • Abstract
    The SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically allocates tasks on the heterogeneous cores and schedules the data transfers through the DMA engines. SARC´s programming model supports various highly parallel applications, with matching support from specialized accelerator processors.
  • Keywords
    "Parallel processing","Runtime","Programming","Multicore processing","Decoding","System-on-a-chip"
  • Journal_Title
    IEEE Micro
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2010.79
  • Filename
    5567090
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3848622