Delay variation tolerant clock scheduling for semi-synchronous circuits

In semi-synchronous framework, the clock is assumed to be distributed periodically to each individual register though not necessarily to all registers simultaneously. It seemed that the effect of delay variation caused by manufacturing and environment variations is more serious than that in a conventional synchronous framework. In this paper, we show a sufficient condition that a circuit works correctly under global delay variation with the delay model that signal propagation delay is the sum of gate delay and routing delay. Using the sufficient condition, we propose a clock scheduling method that guarantees a circuit works correctly within an allowable global delay variation. In experiments, the minimum clock period of a circuit is reduced about 20% compared with conventional synchronous framework even though the circuit behavior is guaranteed in a large global delay variation.