A Bio-Inspired Technique for Energy-Aware FPGAs on Body Area Networks

The usage of Field Programmable Gate Arrays (FPGAs) in resource-constrained devices depends on energy consumption optimization techniques. Existing techniques to reduce FPGA´s energy consumption have been based on several levels of abstraction, from new transistor technologies to mapping algorithms present in circuit CAD tools. However, those techniques often fail to integrate in the CAD flow a multi-step optimization. This work proposes a bio-inspired technique, called AntES (plAcement, pipeliNing and reTiming for Energy Saving), that integrates the FPGA CAD flow joining placement, pipelining and retiming steps in order to reduce energy consumption for supporting BANs. The AntES placement performance is compared with the original VPR placement in terms of power dissipation, critical path delay and bounding box size. Results show energy consumption reduction under several benchmarks, except for the largest sequential circuits.