• DocumentCode
    386722
  • Title

    Optimal MAC structures in an FPGA

  • Author

    du Plessis, Warren P.

  • Author_Institution
    Dept. of Electron. & Comput. Eng., Pretoria Univ., South Africa
  • Volume
    1
  • fYear
    2002
  • fDate
    2-4 Oct. 2002
  • Firstpage
    333
  • Abstract
    Field programmable gate arrays (FPGA) are rapidly gaining popularity for signal processing applications. Multiplication, addition and multiply-accumulate (MAC) are the most important building blocks in signal processing. This paper compares a number of structures to find the optimum configurations for minimum delay, size and cost in an FPGA.
  • Keywords
    adders; digital signal processing chips; field programmable gate arrays; multiplying circuits; DSP systems; FPGA; adders; addition; field programmable gate arrays; multiplication; multipliers; multiply-accumulate; optimal MAC structures; optimum configurations; signal processing applications; Application software; Array signal processing; Clocks; Costs; Delay; Digital signal processing; Field programmable gate arrays; Finite impulse response filter; Hardware; Logic arrays;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Africon Conference in Africa, 2002. IEEE AFRICON. 6th
  • Print_ISBN
    0-7803-7570-X
  • Type

    conf

  • DOI
    10.1109/AFRCON.2002.1146858
  • Filename
    1146858
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=386722