DocumentCode
387200
Title
A minimal source-synchronous interface
Author
Chakraborty, Ajanta ; Greenstreet, Mark R.
Author_Institution
Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
fYear
2002
fDate
25-28 Sept. 2002
Firstpage
443
Lastpage
447
Abstract
We present a novel implementation of source synchronous communication for communication between clock domains within a SOC. Our design appears to the designer as a latch with two clock inputs, one from the transmitter and the other from the receiver. Our circuit is simple and provides a skew tolerance of nearly two clock periods. The analog dynamics of our circuit provide a simple initialization mechanism that maximizes the robustness of the interface to skew variations.
Keywords
computer interfaces; flip-flops; integrated circuit design; integrated circuit interconnections; logic design; synchronisation; system-on-chip; timing; FIFO; SOC inter-clock domain communication; clock periods; clock skew tolerance; data latches; initialization mechanisms; interface skew variation robustness; minimal source-synchronous interfaces; source synchronous communication; transmitter/receiver latch clock inputs; Circuits; Clocks; Communication system control; Computer science; Delay; Latches; Signal generators; System-on-a-chip; Timing; Transmitters;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC/SOC Conference, 2002. 15th Annual IEEE International
Print_ISBN
0-7803-7494-0
Type
conf
DOI
10.1109/ASIC.2002.1158100
Filename
1158100
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