DocumentCode
387637
Title
Topologically constrained logic synthesis
Author
Sinha, Subamarekha ; Mishchenko, Alan ; Brayton, Robert K.
Author_Institution
California Univ., Berkeley, CA, USA
fYear
2002
fDate
10-14 Nov. 2002
Firstpage
679
Lastpage
686
Abstract
SPFDs (sets of pairs of functions to be distinguished), a mechanism for expressing flexibility during logic synthesis, were first introduced for FPGA synthesis. They were then extended to general, combinational Boolean networks and later the concept of sequential SPFDs was introduced. In this paper, we explore the idea of using SPFDs for functional decomposition. A new type of functional decomposition called topologically constrained decomposition is introduced. An algorithm is provided for solving this problem using SPFDs. Preliminary experimental results are encouraging and indicate the feasibility of the approach. A scheme is also presented for generating instances of the topologically constrained decomposition problem.
Keywords
Boolean functions; circuit CAD; combinational circuits; field programmable gate arrays; integrated circuit design; logic CAD; network topology; FPGA synthesis; combinational Boolean networks; distinguished function pair sets; functional decomposition; sequential SPFD; topologically constrained decomposition; topologically constrained logic synthesis; Boolean functions; Circuit synthesis; Data structures; Equations; Erbium; Logic functions; Matrix decomposition; Sufficient conditions;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on
ISSN
1092-3152
Print_ISBN
0-7803-7607-2
Type
conf
DOI
10.1109/ICCAD.2002.1167605
Filename
1167605
Link To Document