2-D Array processor having a controlled pipelined architecture for elliptical sparse matrices

Large block circulant sparse matrices whose submatrices have all non-zero elements within an elliptical or general closed strip, appear in Tomographic image reconstruction from projections. A new 2-D array architecture which fully exploits these features is introduced for the iterative solution of linear systems involving such matrices. Each sub row-vector product is computed in parallel by one row of simple processing units and pipelined to give a high utilisation ratio. A two level controller is used having one Main Control Unit (MCU) and identical simple Sub-Control Units (SCU) - one for each row of the array. This allows appropriate flow of the data and partial products, which in effect split and straighten the elliptical strip to produce two strip diagonal matrices. The VLSI designs for the MCU and SCU have been completed.