Efficient architectures for implementing the prime-factor Fourier transform modules

Memory intensive architectures are highly suited to VLSI technology. In this paper we present efficient architectures for implementing the discrete Fourier transform (DFT) and the discrete Hartley transform (DHART) based on prime factor decomposition. We use the multiplier-less distributed arithmetic in our architecture. But the look-up table sizes needed for implementing the short DFT/DHART modules are minimized by judiciously decomposing the short DFT/DHART matrices.