Circuits for digital signal processing

This paper discusses two custom integrated circuits designed to perform the functions of signal correlation and lattice filtering (MA or AR). Each circuit is decomposed into P operators, each being a direct implementation of the equations. To allow concurrent use of an arbitrary number of operators and to simplify inter-module connections (both within and between chips), a bit-serial architecture was adopted. These chips can be cascaded; computation speed is independent of model order in both types of calculations. These chips have been designed to operate at a sample frequency between 0 and 300 kHz for the correlator, 0 and 150 kHz for the lattice filter.