Effects of process variation on signal integrity for high speed differential signaling on package level

Author

Ahn, Seungyoung ; Lu, Albert Chee W ; Fan, Wei ; Wai, Lai L. ; Kim, Joungho

Author_Institution

Terahertz Interconnection & Package Lab., Korea Adv. Inst. of Sci. & Technol., South Korea

fYear

2002

fDate

10-12 Dec. 2002

Firstpage

249

Lastpage

252

Abstract

This paper presents the effects of the manufacturing process variation on the signal integrity of differential interconnects on package level structure. We have shown that the variation of the manufacturing process has a critical impact on the signal integrity of the differential lines, which results in significant distortion of the transmitted waveform. We have conducted full wave simulation, circuit simulation based on equations, and measurement using TDR system to investigate the relationship between process variation and signal integrity with electrical characteristic parameter analysis.

Keywords

circuit simulation; network parameters; packaging; TDR system; circuit simulation; electrical characteristic parameter analysis; full wave simulation; high speed differential signaling; manufacturing process variation; package level; package level structure; process variation; signal integrity; transmitted waveform; Analytical models; Circuit simulation; Distortion measurement; Electric variables; Electric variables measurement; Equations; Integrated circuit interconnections; Manufacturing processes; Packaging; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging Technology Conference, 2002. 4th

Print_ISBN

0-7803-7435-5

Type

conf

DOI

10.1109/EPTC.2002.1185676

Filename

1185676