On the feasibility of cascaded single-stage distributed amplifier topology in digital CMOS technology

Author

Worapishet, Apisak ; Srisathit, Sarayut ; Chongcheawchamnan, Mitchai

Author_Institution

Microelectron. Res. Centre, Mahanakorn Univ. of Technol., Bangkok, Thailand

Volume

2

fYear

2002

fDate

4-7 Aug. 2002

Abstract

Feasibility of the cascaded single-stage distributed amplifier (CSDA) structure over the classical distributed amplifier for ultra broadband amplification in CMOS technology is investigated in this paper. A number of unique benefits gained from the CMOS CSDA are highlighted along with some important analysis and helpful design hints. Designed and simulated in standard digital 3.3V 0.35μm CMOS process with realistic parasitic models, a prototype design of a 4-stage CMOS CSDA provides 21dB power gain at 5GHz bandwidth, more than -10dB input/output return loss, larger than -7.3dBm 3rd-order input intercept point (IIP3) and dissipates less than 132mW from a 2.2V power supply.

Keywords

CMOS analogue integrated circuits; cascade networks; distributed amplifiers; wideband amplifiers; -10 dB; 0.35 micron; 132 mW; 2.2 V; 21 dB; 3.3 V; 5 GHz; cascaded single-stage distributed amplifier topology; digital CMOS technology; input/output return loss; parasitic model; power dissipation; power gain; third-order input intercept point; ultra-broadband amplification; Bandwidth; CMOS process; CMOS technology; Capacitance; Circuits; Distributed amplifiers; Gallium arsenide; Impedance; Inductors; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on

Print_ISBN

0-7803-7523-8

Type

conf

DOI

10.1109/MWSCAS.2002.1186846

Filename

1186846