An efficient asynchronous pipeline FIFO for low-power applications

In this paper, an efficient micropipeline FIFO for low-power applications is introduced. In this FIFO, instead of using a latch in each stage, an inverter gate with a weak keeper is utilized. This leads to a significant reduction in the number of transistors and the power consumed by the circuit. To demonstrate the efficiency of the design, a 16-bit 4-stage FIFO with four-phase micropipeline control is designed using this approach and a traditional style which uses latches in each stage of the FIFO. The number of transistors is reduced more than 43 percent. The designs are then simulated using HSPICE with 0.6μm CMOS parameters. The results of the power consumption show a power reduction of more than 72 percent.