Offset removal from floating gate differential amplifiers and mixers

A typical differential-pair circuit has an inherent offset between the two input terminals. We show the removal of offsets due to transistor mismatch in circuits based on a differential pair topology, using floating-gate devices at the inputs of the differential pair. This offset causes non-linearities and second-order distortions in the output. By removing the offsets, we show the output to be very linear over a wide dynamic range, and effectively reduce the second order harmonics for a differential pair circuit. Further analysis is shown for a multiplier cell using the floating gate differential pair. We present an architecture to allow the offset reduction of many multiple differential pair elements via an automatic programming element. This architecture allows the use of multiple floating-gate differential pairs with minimal time required to program the offset ification, minimization of I/O pins required for programming, and reduction of complexity and design time in a system.