The delay estimation of critical path in layout design

As integrated circuit (IC) technology moves into deep sub-micron (DSM) and very large scale integration, the design patterns of ICs are transferring. Devices and interconnects play equal attention to layout design instead of devices only. Timing-driven optimization design is a trend for IC design and delay estimation of interconnects has been a part of layout design optimization process. Traditional delay analysis and verification methodologies for critical paths typically were usually based on RC model. However, they are not accurate any more for layout design of VLSI under DSM. With the further development of technology, one of key problems to assure successful design is how to get a good trade-off between efficiency and precision so that it can be use in layout design. It is also important to choose a fine calculation method of the equivalent circuit parameters because its calculation precision directly affects the reliability of delay results. In this paper an approach is presented to estimate the propagation delay of critical path in layout design by circuit iterative equivalence which assures the precision and improves the efficiency greatly.