DocumentCode
395028
Title
Input/output complexity of bit-level VLSI array architectures
Author
Burleson, Wayne P. ; Scharf, Louis L.
Author_Institution
University of Colorado
Volume
1
fYear
1989
fDate
1989
Firstpage
426
Lastpage
430
Keywords
Array signal processing; Computer architecture; Computer interfaces; Delay; Digital signal processing; Electronics packaging; Hardware; Iterative algorithms; Signal processing algorithms; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 1989. Twenty-Third Asilomar Conference on
Print_ISBN
0-929029-30-1
Type
conf
DOI
10.1109/ACSSC.1989.1200826
Filename
1200826
Link To Document