Parallel high-speed architecture for EBCOT in JPEG2000

In this paper, a parallel high-speed architecture for EBCOT is proposed, based on the parallel mode in JPEG2000. It discovers the parallelism among three passes in bit-plane coding: two passes can work on the coding operation without the addition of coding processing elements (PE) by using parallel context modeling. So it manages to make two bits encoded in one clock cycle. In order to keep high throughput and reduce the memory requirement, the pipelined pass-switching arithmetic encoder is adopted. The experimental results show that the proposed architecture reduces the processing time by more than 16.6% compared with the pass-parallel mode architecture in Chiang et al. (2002) and by more than 38% compared with the serial mode architecture in Chen et al. (2001).