An improved parallel architecture for MPEG-4 motion estimation in 3G mobile applications

Author

Xu, Donglai ; Gao, Rui ; Batatia, Hadj

Author_Institution

Teeside Univ., Middlesbrough, UK

Volume

2

fYear

2003

fDate

6-10 April 2003

Abstract

A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, a full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth.

Keywords

3G mobile communication; VLSI; buffer storage; image matching; image sequences; mobile radio; motion estimation; multimedia communication; parallel architectures; trees (mathematics); 1 MHz; 15.5 Mbyte/s; 3G mobile applications; MPEG-4 motion estimation; QCIF video sequences; VLSI core architecture; dual-register/buffer technique; full-search block matching algorithm; low clock rate; low memory bandwidth; mobile multimedia; parallel architecture; tree architecture; Bandwidth; Clocks; Computer architecture; MPEG 4 Standard; Motion estimation; Streaming media; Very large scale integration; Video compression; Video sequences; Videoconference;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03). 2003 IEEE International Conference on

ISSN

1520-6149

Print_ISBN

0-7803-7663-3

Type

conf

DOI

10.1109/ICASSP.2003.1202460

Filename

1202460