Pulse extraction: a digital power spectrum estimation method for adaptation of Gbps equalizers

This paper presents a new method to estimate the power spectrum of a digital signal, which is used to generate an error signal to tune the FIR filter in a Gbps data rate adaptive equalizer for digital communication. The proposed error detection circuit is composed of standard digital logic circuit and a phase lock loop (PLL), thus it is scalable to higher-speed processes beyond the GHz range. Matlab simulation shows that the proposed method can achieve the same bit error rate performance with the one using a bandpass filter to estimate the power spectrum, but with largely reduced power dissipation and chip area. Fabricated in TSMC CMOS 0.35 μm technology, the pulse extractor and its tuning circuit occupy 0.075 mm².