An ultra-low power double-sampled A/D MASH ΣΔ modulator

Author

Le Révérend, Rémi ; Kale, Izzet ; Guy, D. ; Morling, Dik ; Morris, Steve

Author_Institution

ZARLINK Semicond., Inc, San Diego, CA, USA

Volume

1

fYear

2003

fDate

25-28 May 2003

Abstract

A low power switched-capacitor third-order 2-1 MASH ΣΔ modulator is presented showing how both architecture and implementation techniques are used to achieve the power, dynamic range and SNR design objectives. This structure is part of a chip set designed for ultra-low-power audio applications and uses a low V_T, 0.35μm CMOS process allowing operation over a supply range of 1V to 1.5V and with a typical current consumption of I_dd=60μA, maintaining performance for V_dd down to 0.8V. The measured dynamic range and peak SNR of the modulator are 82dB and 64dB respectively over an 8kHz bandwidth and with an Over Sampling Ratio (OSR) of 64.

Keywords

CMOS integrated circuits; low-power electronics; sigma-delta modulation; switched capacitor networks; 0.35 micron; 1 to 1.5 V; 60 muA; 8 kHz; CMOS process; Over Sampling Ratio; SNR design; current consumption; double-sampled A/D MASH ΣΔ modulator; dynamic range; low power switched-capacitor modulator; third-order modulator; ultra-low-power audio applications; Bandwidth; Capacitors; Circuit simulation; Delta modulation; Digital signal processing; Dynamic range; Mathematical model; Multi-stage noise shaping; Power semiconductor switches; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205735

Filename

1205735