A 1.4G samples/sec comb filter design for decimation of sigma-delta modulator output

Author

Kim, Daeik D. ; Brooke, Martin A.

Author_Institution

Georgia Inst. of Technol., Atlanta, GA, USA

Volume

1

fYear

2003

fDate

25-28 May 2003

Abstract

A new architecture of high-speed comb filter is proposed and simulated. The proposed architecture takes advantage of the concept of carry-save adder and binary signed-digit to minimizes the carry propagation. It has a highly modular architecture and can be used for any order and any word length of comb filter. Also the concept can be applied to the optimization of a general high-speed adder or accumulator. The simulation of the proposed filter can process 1.4G samples/sec when it is designed using a 0.18μm standard CMOS process. The chip area is 360μm by 140μm. The same architecture can run at 120M samples/sec using a 1.5μm CMOS process and takes 3360μm by 1630μm in chip area. Discussion and suggestion related to the common comb filter algorithm is also presented.

Keywords

CMOS integrated circuits; adders; carry logic; comb filters; high-speed integrated circuits; sigma-delta modulation; 0.18 micron; 1.5 micron; binary signed-digit; carry propagation; carry-save adder; chip area; comb filter design; decimation; high-speed filter; optimization; sigma-delta modulator output; Adders; Band pass filters; Circuit noise; Delta-sigma modulation; Equations; Finite impulse response filter; IIR filters; Noise shaping; Sampling methods; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205737

Filename

1205737