A design methodology for power-efficient continuous-time ΣΔ A/D converters

Author

Nielsen, Jannik Hammel ; Bruun, Erik

Author_Institution

Tech. Univ. Denmark, Lyngby, Denmark

Volume

1

fYear

2003

fDate

25-28 May 2003

Abstract

In this paper we present a design methodology for optimizing the power consumption of continuous-time (CT) ΣΔ A/D converters. A method for performance prediction for ΣΔ A/D converters is presented. Estimation of analog and digital power consumption is derived and employed to predict the most power efficient configuration of a CT single-loop ΣΔ ADC. Finally, a 10 bit prototype converter is optimized and simulated using a 0.35 μm CMOS technology. The simulation results of the prototype 1.8 V converter show a SNR better than 65 dB and a spurious-free dynamic range of more than 63dB, consistent with 10 bits performance. Expected power consumption for the prototype is approx. 170 μW.

Keywords

CMOS integrated circuits; continuous time systems; sigma-delta modulation; 0.35 micron; 1.8 V; 10 bit; 170 muW; CMOS; CT single-loop ADC; SNR; design methodology; performance prediction; power efficient configuration; power-efficient continuous-time ΣΔ A/D converters; spurious-free dynamic range; Design methodology; Design optimization; Dynamic range; Energy consumption; Feedback; Filters; Frequency; Sampling methods; Transfer functions; Virtual prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205752

Filename

1205752