A 2GHz image-reject receiver in a low IF architecture fabricated in a 0.1 μm CMOS technology

This work describes a 2GHz wideband receiver which is aimed for wireless applications. It consists of an LNA and a complex mixer in a low IF architecture. The receiver is implemented in a CMOS development process where the device dimensions are scaled to 0.1μm which is beyond today´s commercially available CMOS technologies. The design emphasizes image rejection, low-voltage and low-power aspects. The pros and cons of a low IF architecture are addressed. The quality of the receiver is discussed in terms of noise figure, power gain, power consumption, image rejection and 1-dB compression. Measurements show that on-chip calibration for the phase imbalance in the quadrature signal path results in a significant suppression of the image signal of 52dB. The supply voltage is 1.2V. In order to lower the power consumption the RF blocks are operating close to the weak-inversion region, resulting in a power consumption of 25 mW. To further suppress the image signal, a similar receiver architecture including a complex filter is suggested. Such a filter is also realized in this work.