Advanced CMOS device sensitivity to USJ processes and the required accuracy of doping and activation

Device performance variability and yield depend to a large extent on the accuracy of processing tools and the sensitivity of the devices to process variations. The device sensitivity to process variation increases with device shrinking and hence mandates higher accuracy on the processing tools. In this study we applied USJ (ultra shallow junction) module equipment by Applied Materials for the most advanced CMOS LOGIC devices provided by Toshiba to study the device sensitivity to USJ processes including both implant and annealing parameters. NMOS and PMOS devices with gate length of below 100 nm were used to determine the accuracy and the purity needed for sub keV implant energy, accuracy of dose, within wafer uniformity and wafer to wafer repeatability of spike anneal peak temperature and the ramp up and cool down rates. The implant and the anneal work were done on the Applied Materials Quantum Leap implanter and Radiance RTP. Various features including junction depth (x_j), sheet resistance and other device parameters are examined in order to quantify the sensitivity of each parameter to implant and anneal conditions. From these results we determined the required accuracy, uniformity and repeatability for the implant and the annealing tools for less than 100 nm node CMOS devices.