A real-time reconfigurable pipelined architecture with advanced power management for UTRA-FDD

A reconfigurable-pipelined architecture with advanced power management has been proposed for a mobile terminal receiver that can reduce power dissipation. The design can automatically scale the number of filter coefficients and word length respectively by monitoring the in-band and out-of- band powers. The new architecture performance was evaluated in a simulation UTRA-FDD environment. A power consumption analysis of the implemented architecture is also presented. The UTRA-FDD downlink mode was examined statistically and results show that the reconfigurable architecture can save an average 70 percent power dissipation when compared to a fixed filter length of 41 and ADC word length of 16 bits. This will prolong talk and standby time in a mobile terminal. The average number of taps and bits were calculated to be 11 and 7 respectively.