Timing signoff uncertainty for UDSM SoC design

Ultra-Deep Sub-Micron (UDSM) technology posts a serious challenge to the chip designer and EDA tools on the timing signoff accuracy. Timing signoff uncertainty due to in-die process variation, environmental variation, extraction accuracy and timing modeling accuracy become concerns for the timing signoff of UDSM SoC design. Traditional worst/best case timing sign-off methodology can cover the systematic process variation but can not model the in-die variation and environmental variation effects. On-chip-Variation timing analysis is now widely adopted to improve the design robustness under the consideration of timing signoff uncertainty. In this paper, we will present a case study of a 0.13 μm million gates SoC design on the various UDSM effects on timing signoff accuracy.