A routing algorithm of clock distribution circuit of high frequency

In this paper a method of routing of clock distribution circuits will be presented. We first give out the background of the problem we later studied. In this section, we discuss the three constrains of the routing on a clock distribution chip. Then we offer an algorithm to solve this problem. The algorithm features in 3 steps, which are called topology generation, cut line generation and the adjustment process. We will further develop the 3 steps into more details in the following 3 sections. And in latter part some application samples are shown to evaluate the algorithm. Finally we concluded the further work we should probe into.