Design and implementation of an new Built-In Self-Test boundary scan architecture

Author

El-mahlawy, Mohamed H. ; El-sehely, Ehab A. ; Ragab, Ai-emam S. ; Anas, Sherif

fYear

2003

fDate

9-11 Dec. 2003

Firstpage

27

Lastpage

31

Abstract

The boundary scan (BS) technique offers a convenient alternative to physical probing. This paper presents new boundary scan architecture for Built-In Self-Test (BIST). The Boundary Scan Register (BSR) input cells have been configured to operate as a Test Pattern Generator (TPG) in the BIST mode. The BSR output cells have been configured to operate as a Multi-Input Shift Register (MISR) In the BIST mode. The Test Access Port Controller (TAPC) controls the BIST process. Instructions for BIST process are proposed. This configuration supports the BIST for both the Built-In Logic Block Observer (BILBO) register and the register transfer level. This design Implemented on the Field Programmable Gate Array (FPGA) Spartan X2C200 family.

Keywords

boundary scan testing; built-in self test; field programmable gate arrays; shift registers; BILBO register; BIST; FPGA; boundary scan architecture; boundary scan register; built in self test boundary; built-in logic block observer register; field programmable gate array; multi-input shift register; register transfer level; test access port controller; Automatic testing; Built-in self-test; Circuit testing; Field programmable gate arrays; Logic testing; Pins; Process control; Programmable logic arrays; Registers; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2003. ICM 2003. Proceedings of the 15th International Conference on

Print_ISBN

977-05-2010-1

Type

conf

DOI

10.1109/ICM.2003.1287714

Filename

1287714