Bolstering faith in GasP circuits through formal verification

We propose a refinement-based technique to formally verify circuits of the GasP family. Verifying GasP circuits presents two main challenges: exploit their highly modular structure to reduce verification costs, and express formally their unconventional behavior at the low level, such as bidirectional signals, self-resetting logic, and fights. We propose a novel semi-automated technique for constructing specification models for interfaces of GasP circuit control units, which synchronize single-track handshake signals from different channels. These specifications are captured at a high level using abridged data transition events and transformed into intermediate specifications using low-level signal transition events. High-level verifications using data transition events are exact if each unit conforms to its intermediate specification. As a case study, we verify that a set of relative timing constraints inside the units and along channels between units, consistent with the original sizing of the circuits, is sufficient to guarantee correctness of a previously proposed square FIFO.