Design-space exploration of a cryptography algorithm

Network data is, currently, often encrypted at a low level. In addition, the majority of future networks will use low-layer (IP level) encryption. Current trends imply that future networks are likely to be dominated by mobile terminals, and thus the power consumption and electromagnetic emissions aspects of encryption devices will be critical. This paper presents several realisations of the DES algorithm, both in software and in hardware. We present software implementations of the algorithm running on the state-of-the-art Intel IXP network processor and seven hardware realisations based on a standard-cell library. Three of our hardware realisations are conventional clocked designs, where the other four are asynchronous. We demonstrate that the most efficient realisation of the algorithm is a hardware implementation, and indeed an asynchronous one.