Compensation of a winner take all circuit

Author

Kothapalli, Ganesh

Author_Institution

Edith Cowan Univ., Perth, WA, Australia

Volume

1

fYear

2003

fDate

14-17 Dec. 2003

Firstpage

352

Abstract

The design and simulation results of a CMOS winner-take-all (WTA) circuit are presented. A 16-cell test circuit has been designed for intended implementation in an 0.18 μm CMOS process. This paper describes the architecture and design issues related to a CMOS WTA circuit. Several design issues such as high resolution, high speed, low power consumption, compactness, and high input voltage range have been addressed. The proposed circuit has a compact configuration of complexity O(N) where N denotes input count. It seems to be very suitable, especially for charge-based applications where input vectors are generated by a set of charged capacitances.

Keywords

CMOS analogue integrated circuits; circuit simulation; compensation; current mirrors; current-mode circuits; low-power electronics; 0.18 micron; CMOS WTA circuit; WTA resolution; charge-based applications; charged capacitance generated input vectors; current mirror; input voltage range; low power consumption; winner take all circuit compensation; CMOS process; Capacitance; Circuit simulation; Circuit testing; Energy consumption; MOSFETs; Mirrors; Neural networks; Neurons; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on

Print_ISBN

0-7803-8163-7

Type

conf

DOI

10.1109/ICECS.2003.1302049

Filename

1302049