Low-density parity-check code constructions for hardware implementation

We present several hardware architectures to implement low-density parity-check (LDPC) decoders for codes constructed with a hierarchical structure. The proposed hierarchical formulation of the LDPC code allows a structured hardware realization of the decoder. For a fully-parallel implementation, there is a reduced routing congestion that allows implementations for blocks sizes up to 1024 bits in 0.13μm technology. Partially and fully serial implementations benefits greatly from the structure of the code as well, leading to several flexible, efficient architectures. In a general purpose 0.13μm technology, the approximate area required by a 1024-bit fully-parallel LDPC decoder is found to be 12.5 mm² while a serial decoder can be implemented in an area of 0.15 mm².