• DocumentCode
    416319
  • Title

    Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects

  • Author

    Changbo Long ; Simonson, Lucanus J. ; Liao, Weiping ; He, Lei

  • Author_Institution
    University of California, Los Angeles, CA
  • fYear
    2004
  • fDate
    7-11 July 2004
  • Firstpage
    640
  • Lastpage
    645
  • Keywords
    Algorithm design and analysis; Clocks; Delay; Integrated circuit interconnections; Microprocessors; Permission; Piecewise linear techniques; Pipeline processing; System performance; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2004. Proceedings. 41st
  • Conference_Location
    San Diego, CA, USA
  • ISSN
    0738-100X
  • Print_ISBN
    1-51183-828-8
  • Type

    conf

  • Filename
    1322562
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=416319