Power consumption optimization for low latency Viterbi Decoder

Viterbi Decoder applications with severe latency constraints are recently emerging. OFDM based WLAN 802.11 a/g is one example where not throughput but latency is challenging. A Viterbi Decoder using register-exchange path history memory only needs the systematic latency introduced by the decision depth for hard decision. Unfortunately this architecture is critical in terms of power consumption. This paper describes the measures taken to reduce power consumption under the given latency constraint.