The noise immunity of dynamic digital circuits with technology scaling

Author

Mendoza-Hernandez, F. ; Linares, M. ; Champac, V.H.

Author_Institution

Dept. of Phys. Investigation, Sonora Univ., Mexico

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

Signal integrity issues are a main concern in high performance circuits due to the higher clock rates and the increased integration complexity. Interconnect scaling is also playing an important role in this problem. In this paper, the noise immunity of dynamic digital circuits, as the technology scales, is investigated by means of simulations using a reliable scaling scenario. An analytical expression for the noise immunity of dynamic circuits is also used in the analysis. Conventional and noise-tolerant circuits have been considered. Simulation and analytical results confirm that the noise immunity of dynamic circuits decreases with technology scaling.

Keywords

SPICE; circuit complexity; crosstalk; digital circuits; electromagnetic compatibility; integrated circuit interconnections; interference suppression; scaling circuits; clock rates; dynamic digital circuits; integration complexity; interconnect scaling; noise immunity; noise-tolerant circuits; reliable scaling scenario; signal integrity; simulation program with integrated circuit emphasis; Capacitance; Circuit noise; Circuit simulation; Crosstalk; Delay; Digital circuits; Dynamic voltage scaling; Integrated circuit interconnections; Logic; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329316

Filename

1329316